# Space Vectors Modulation for Nine Switch Inverter Essay

NO. 6, JUNE 2010 Space Vectors Modulation for Nine-Switch Converters Seyed Mohammad Dehghan Dehnavi, Student Member, IEEE, Mustafa Mohamadian, Member, IEEE, Ali Yazdian, Member, IEEE, and Farhad Ashrafzadeh, Senior Member, IEEE Abstract—Recently, nine-switch inverter and nine-switch-zsource inverter have been proposed as dual output inverters. In this paper, the space vector modulation (SVM) of nine-switch inverter and nine-switch-z-source inverter is proposed.The proposed method increases the sum of modulation indices up to 15% in contrast with the conventional, scheme in which the sum of modulation indices is equal or less than one. The extra voltage available for a given input dc-voltage, translates to a higher torque—a critical factor for de? ning the capacity of products in marketplace.

Also, in order to further reduce the cost of power devices and also thermal heat effect, and to reduce the number of semiconductor switching, speci? c SVM switching pattern is presented. This feature will be advantageous for high-power inverter applications where cost and ef? iency are key decision factors. Furthermore, a novel SVM is proposed for minimizing total harmonic distortion. The performance of the proposed SVM for both nine-switch inverter and nine-switch-z-source inverter is veri? ed by simulation. Experimental results validate the simulation results as well as the superiority of the proposed SVM. Fig. 1. Nine-switch inverter.

Fig. 2. Nine-switch-z-source inverter.

Index Terms—Nine-switch inverter, nine-switch-z-source inverter, space vector modulation (SVM). I. INTRODUCTION NVERTERS are used as dc/ac converter and power controller or ac load such as motor drivers. In many cases, there are two or more ac loads, which require independent control. The conventional solution is to use separate inverters. This increases cost and volume of system. A dual output inverter has been presented in [1] using only nine semiconductor switches (see Fig.

1). This inverter is known as nine-switch inverter and is also used as an ac/ac converter in [2] and [3]. The nine-switch inverter is composed of two conventional inverters with three common switches. In nine-switch inverter, sum of modulation index of two outputs must be less than or equal to one.Therefore, voltage amplitude of outputs is smaller, compared with two separate inverters [4].

To remedy this problem, this paper proposes using an impedance source (z-source) network in front of nine-switch inverter as a dc/dc boost converter (see Fig. 2). Z-source network was used as front-end boost converter for a conventional inverter in [5], for the ? rst time. This inverter was called z-source inverter and has been proposed for fuel cell, photovoltaic, and wind I Manuscript received April 21, 2009; revised July 25, 2009 and August 30, 2009. Current version published June 3, 2010. Recommended for publication by Associate Editor J.

R. Rodriguez. S. M. Dehghan Dehnavi, M. Mohamadian, and A.

Yazdian are with the Department of Electrical and Computer Engineering, Tarbiat Modares University, Tehran 14115-143, Iran (e-mail: [email protected] ac. ir; [email protected] ac.

ir; [email protected] ac. ir). F. Ashrafzadeh is with the Research and Engineering Center, Whirlpool Corporation, Benton Harbor, MI 49022 USA (e-mail: Farhad. [email protected] ieee.

org). Digital Object Identi? er 10. 1109/TPEL. 2009.

2037001 turbine systems [6]–[8]. The z-source network also was used in other converters such as three-level inverters [9], [10].In [1], carrier-based pulsewidth modulation (PWM) methods have been proposed for nine-switch inverter. This paper proposes space vector modulation (SVM) methods for the aforementioned nine-switch and nine-switch-z-source inverters. In order to reduce number of semiconductor switching and total distortion harmonic (THD), some speci? c switching patterns for SVM are proposed. This paper is organized as follows. Section II describes the carrier-based PWM control method for nine-switch inverter.

Section III describes the proposed SVM for nine-switch inverter, as well as two special SVMs with minimum switching number nd THD. The proposed SVM is developed for nine-switch-zsource inverter in Section IV. Section V describes maximum gain. Finally, Section VI presents simulation and experimental results. II. CARRIER-BASED PWM METHOD The carrier-based PWM control method for nine-switch inverter is shown in Fig. 3.

There are two reference signals (upper and lower) for each phase. The upper and lower reference signals are related to upper and lower outputs respectively. The 0885-8993/$26.

00 © 2010 IEEE Authorized licensed use limited to: Bharat University. Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore.Restrictions apply. DEHGHAN DEHNAVI et al. : SPACE VECTORS MODULATION FOR NINE-SWITCH CONVERTERS 1489 TABLE I SEMICONDUCTORS ON-OFF POSITION OF LEGS Fig. 5. Typical SVM switching vector sequence. TABLE II SVM SWITCHING VECTORS Fig.

3. Fig. 4. Carrier-based PWM method for nine-switch inverter.

Carrier-based PWM method switching vector. gate signal for upper switch of a leg is generated by comparing the carrier signal and upper reference signal of the related phase (Vref U J ). Similarly, the gate signal for lower switch is generated from the carrier signal and lower reference signal of the related phase (Vref L J ).The gate signal for mid switch is generated by the logical XOR of the gate signals for upper and lower switches. With this method, always two switches are ON in each leg.

Fig. 4 shows carrier-based PWM method switching vectors. There are six vectors in each switching cycle for both outputs: two nonzero vectors, one zero vector 0 0 0, two nonezero vectors and one zero vector 1 1 1 {two active—short zero (0 0 0)—two active—long zero (1 1 1)}. In an active vector, output load is connected to the dc input source, while in a zero vector, the output load is short-circuited.When one of the outputs has an active or short zero (0 0 0) vector, the other output has long zero (1 1 1) vector.

III. SVM FOR NINE-SWITCH INVERTER In regard to Fig. 3, each leg can be in three different semiconductors ON-OFF position.

These position can be called {1}, {0}, and {? 1}, as is illustrated in Table I. In Table I, J refers to leg A, B , or C and U , M , L refers to upper, mid, and lower semiconductor, respectively. The combination of switching vector of both outputs in Fig. 4 creates a speci? c sequence as shown in Fig. 5. This sequence is used to design SVM method.There are 12 vectors in each switching cycle: {two upper active (VA U )—zero (VZ )—two upper active (VA U )—zero (VZ )—two lower active (VA L )—zero (VZ )—two lower active (VA L )—zero (VZ )}.

The switching vectors are listed in Table II. The vectors V1 –V6 are upper active vectors. In these vectors, the upper output is in active state, and the lower output is in zero state. There is an inverse logic in lower active vectors (V7 –V12 ). In zero vectors (V13 –V15 ), both outputs are in zero state. Table II does not include all possible variations of switching states {1}, {0}, and {? }.

Since a vector including {? 1} and {0} connects both loads to the dc source at the same time, the loads lose their independence and they cannot have independent frequencies. This is the reason for avoiding a vector that includes combinations of {? 1} and {0}. In none of the switching vectors as listed in Table II, both outputs are not in an active state at the same time. However, in vectors including both {? 1} and {0} such as {? 1, 1, 0}, both outputs are in active state. These vectors are ignored because there are not all combinations of active vectors for both outputs.For example, if upper output be in active vector (1 1 0), lower output can be in vectors (0 0 0), (1 0 0), (0 1 0), or (1 1 0) as shown in Fig. 6. However, vectors (0 1 1), (0 0 1), and (1 0 1) are not available for lower output.

Therefore, outputs cannot be controlled independently. Authorized licensed use limited to: Bharat University. Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply. 1490 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL.

25, NO. 6, JUNE 2010 Fig. 6. Available switching vectors of nine-switch inverter while upper output is in active vector (1 1 0). Fig. .

SVM with reduced number of semiconductor switching. v 3 mU T sin(? U ) 2 v ? 3 mL T sin ? ? L T3 = 2 3 v 3 mL T sin(? L ) T4 = 2 To = T ? T1 ? T2 ? T3 ? T4 T2 = Fig. 7.

Space vector diagrams for nine-switch inverter. (a) Upper output. (b) Lower output.

To determine the proper active vectors, two space vector diagrams are proposed as shown in Fig. 7. The diagrams (a) and (b) are used to determine the upper and lower active vectors, respectively. The SVM active vectors are determined with re? gard to location of upper reference signal (Vref U ) in the diagram ? ref L ) in the diagram (b).

The a) and lower reference signal (V reference signals for the upper and lower outputs are de? ned as ? Vref U = Vref U ? U (1) ? Vref L = Vref L ? L (2) ?U = 2? fU t + ? U (3) ?L = 2? fL t + ? L (4) (6) (7) (8) (9) where T1 , T2 are the time interval of upper active vectors, T3 , T4 are time of lower active vectors, To is time of zero vectors and T is switching period. mU and mL are upper and lower modulation indices, respectively, and de? ned by mU = 2 Vref U Vi (10) mL = 2 Vref L . Vi (11) The sum of active vector time intervals must be less or equals to T . Thus, the following constrain must be satis? d (see Appendix): 2 (mU + mL ) ? v ? 1. 155. 3 (12) where where fU , fL are the frequencies, and ? U , ? L are the phases.

All zero vectors V13 , V14 , and V15 can be used for zero states. The type of zero vectors can be selected based on control goals and optimizations such as minimum number of semiconductor switchings. The switching time intervals of vectors are calculated as v ? 3 mU T sin ? ? U (5) T1 = 2 3 Equation (12) clearly indicates that in the proposed SVM scheme, sum of modulation indices increases about 15%—a very important feature to provide higher torque for a given nput dc-voltage. In the case of washing machines, the above capability translates to higher machine capacity (in terms of cloth load) at high spin speed (e.

g. , 1800 r/min)—an important product feature in marketplace. A switching vector sequence for the proposed SVM is shown in Fig. 8.

This switching sequence is developed to reduce the number of semiconductor switching. The zero vectors are placed just between two upper and lower active vectors. In upper active vectors, legs are in state {1} or {0} and in lower active vectors, Authorized licensed use limited to: Bharat University.

Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply. DEHGHAN DEHNAVI et al. : SPACE VECTORS MODULATION FOR NINE-SWITCH CONVERTERS 1491 TABLE III SHOOT-THROUGH VECTORS OF NINE-SWITCH Z-SOURCE INVERTER Fig. 9. SVM with reduced THD. legs are in state {1} or {? 1}. If V13 zero vector is placed between the active vectors, minimum number of switching is required.

While if V14 or V15 zero vectors are used, number of switching is increased. There are two odd active vectors (V1 , V3 , V5 , V8 , V10 , and V12 ) and two even active vectors (V2 , V4 , V6 , V7 , V9 , and V11 ) in a switching sequence.In an even active vector, two legs are in state {1}, while in an odd active vector only one leg is in state {1}. If even active vectors are placed next to V13 , number of switching will be reduced even more (see Fig.

8). There are other possible switch generation methods too, e. g. , a switching method, to reduce THD. To minimize THD, active vectors for each output should be centrally placed within the switching period [11]. Fig. 9 shows a switching vector sequence that shifts active vector into center of switching period, hence reducing THD. In this sequence, zero vectors are inserted between active vectors.

In Fig. 9, V14 is inserted between upper active vectors and V15 is inserted between lower active vectors. ON-OFF TABLE IV POSITION OF SEMICONDUCTOR SWITCHES IN STATE {2} IV. NINE-SWITCH-Z-SOURCE INVERTER SVM The nine-switch-z-source inverter is shown in Fig. 2. This inverter has an extra z-source network including two inductors (L1 and L2 ), two capacitors (C1 and C2 ) and a diode (D).

The z-source network is similar to a dc/dc boost converter with [12] Vi = B Vo (13) where Vo is input dc voltage and Vi is output of z-source network. B is known as boost factor and is given by following equation: B= 1 ? 2(TSC /T ) (14) where TSC is shoot-through time. In the shoot-through times, the output of z-source network is shorted through the switches of the inverter. During shoot-through state, since the inverter (output of z-source network) is shorted, inverter cannot have an active vector. Therefore a shoot-through state can only occur Fig. 10. Nine-switch-z-source inverter SVM with reduced switching. when the inverter has a zero state.

Table III shows all the vectors that the inverter includes zero state and the z-source network has a shoot-through state. These vectors are known as shootthrough vectors.There is a new state (state {2}) in Table III. The ON-OFF position of switches of a leg in state {2} is shown in Table IV. All vectors of Table III can be used for generating a shoot-through state.

Fig. 10 shows a SVM vector sequence for nine-switch inverter with reduced number of switching. The sequence is a modi? ed version of Fig. 8. Two shoot-through vectors are placed in both sides of zero vector (V13 ). Here, the shoot-through vector close to upper active vector is called upper shoot-through vector (VSCU ) and the shoot-through vector close to lower Authorized licensed use limited to: Bharat University.Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore.

Restrictions apply. 1492 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 TABLE V DETERMINING UPPER AND LOWER SHOOT-THROUGH VECTOR WITH REDUCED NUMBER OF SWITCHING TABLE VI DETERMINING UPPER AND LOWER SHOOT-THROUGH VECTOR WITH REDUCED THD According to (12), in nine-switch inverter, sum of modulation indices should be smaller than 1. 15. If the same amplitude for both ac outputs is desired, we have Vi Vac U m a x = Vac L m a x = v . 23 (17) If amplitude of one of the outputs is set to zero, maximum amplitude of other output can be increasedVi Vac m a x = v 3 (18) For nine-switch-z-source inverter, the magnitude of peak phase voltage of ac outputs can be expressed by Vo 2 Vo = BmL .

2 Vac U = BmU Nine-switch-z-source inverter SVM with reduced THD. active vector is called lower shoot-through vector (VSCL ). All vectors listed in Table III can be used as the upper and lower shoot-through vectors. However, vectors V27 , V30 , and V33 are preferred because those vectors have only one state {2} and need less switching.

As shown in Fig. 10, even active vectors are placed close to shoot-through vectors (the reason described in Section III).In even active vectors, two legs are in state {1} and one leg is in state {0} or {? 1}. On other hand, in shootthrough vectors V27 , V30 , and V33 , two legs are in state {1} and one leg is in state {2}. To reduce the number of switching, the two legs in state {1} must have the same state in an even active vector and shoot-through vector close to it. Table V can be used for shoot-through vectors selection. For reducing THD, switching sequence shown in Fig. 11 is developed for nine-switch-z-source inverter.

Similar to Fig. 9, zero vectors and shoot-through vectors are inserted between imilar active vectors. Table VI can be used for shoot-through vector selection with reduced THD. GU = BmU Vac L (21) GL = BmL . (22) Boost factor is limited by voltage rating of semiconductor switches (VS ). For a given voltage rating, maximum boost factor can be calculated by Bm ax = VS . Vo (23) Maximum voltage gain is determined by: Gm ax = Bm ax mm ax B (24) where mm ax B is the maximum possible modulation index, when B is at its maximum value.

If the same amplitude for both ac outputs is desired mm ax B can be calculated by 1 mm ax B = v (1/Bm ax + 1) . 23 (25) (15) 1Gm ax = v (Bm ax + 1). 23 (26) (16) If amplitude of one of the outputs is set to zero, maximum possible modulation index for other output can be determined The magnitude of peak phase voltage of ac outputs of nineswitch inverter can be expressed by Vac U (20) The voltage gains can be de? ned by [13] V. MAXIMUM GAIN Vi = mU 2 Vi = mL . 2 (19) Vac L Fig. 11. Thus Authorized licensed use limited to: Bharat University.

Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply. DEHGHAN DEHNAVI et al. : SPACE VECTORS MODULATION FOR NINE-SWITCH CONVERTERS 1493 Fig. 12.

Maximum voltage gain (G m a x ) versus V o (for nine-switch inverter) or V i (for nine-switch-z-source inverter) for a given switch voltage rating (V S ). (a) Nine-switch inverter: equal maximum amplitudes. (b) Nine-switch-z-source inverter: equal maximum amplitudes. (c) Nine-switch inverter: maximum amplitude for one of the outputs. (d) Nine-switch-z-source inverter: maximum amplitude for one of the outputs.

TABLE VII SIMULATION PARAMETERS Fig. 13. (a) Line voltage of nine-switch inverter (simulation). (b) Line voltage of nine-switch inverter (experimental), (50 V/DIV, 10 ms/DIV).

by 1 mm ax B = v 3 1 +1 .Bm ax (27) Thus 1 Gm ax = v (Bm ax + 1). (28) 3 Fig. 12 shows maximum possible voltage gains for a given switch voltage rating. VI. SIMULATIONS AND EXPERIMENTAL RESULTS The proposed SVMs are simulated for nine-switch inverter and nine-switch-z-source inverter. Prototypes of both converters also were built using DSP for verifying the proposed SVMs. Two similar resistive loads with LC ? lters are connected to the outputs of inverter.

Simulation parameters are listed in Table VII. The nine-switch inverter with input dc source of 150 V is simulated and implemented with reduced number of switching SVM. Figs. 3 and 14 show line–line voltage and phase voltage of both outputs, respectively. It can be seen that both outputs have expected frequencies. The load current is shown in Fig.

15. It can be seen that the load currents have nearly sinusoidal waveforms. Fig. 14. (a) Phase voltage of nine-switch inverter (simulation). (b) Phase voltage of nine-switch inverter (Experimental), (50 V/DIV, 10 ms/DIV). In second simulation, a z-source network including L1 = L2 = 2 mH and C1 = C2 = 2. 2 mF was added to nine-switch inverter.

An input dc source of 100 V is used. To boost input voltage to 150 V, TSC /T was set to 0. 166 considering (14).The output of z-source network (Vi ) is shown in Fig.

16. As expected, Vi magnitude changes between 0 and 150 V, respectively. Fig. 17 shows z-source network capacitor voltages. The voltage is equal to expected value of 125 V.

Capacitor voltage is 0. 5 (VO + Vi ), as described in [5]. Figs. 18 and 19 show line–line voltage and Authorized licensed use limited to: Bharat University. Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply.

1494 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 Fig. 17. (a) Capacitor voltage of nine-switch-z-source inverter (simulation). b) Capacitor voltage of nine-switch-z-source inverter (experimental), (50 V/DIV, 1 ms/DIV).

Fig. 15. (a) Output currents of nine-switch inverter (simulation). (b) Output currents of nine-switch inverter (experimental), (2 A/DIV, 10 ms/DIV). Fig. 16. Output voltage of z-source network (simulation). phase voltage of both outputs, respectively.

The load current is seen in Fig. 20. Number of switching of semiconductors for nine-switch inverter and z-source-nine-switch inverter using carrier-based PWM and the proposed SVMs are shown in Table VIII. Number of switching for 0. 1 s with parameters of Table VII is calculated.

As seen in Table VIII, number of switching is considerably reduced using proposed SVMs. Fig. 21 shows THD of load current versus load current magnitude for four different cases: 1) carrier-based PWM, 2) minimum number of switching SVM, 3) reduced THD SVM, and 4) six switch inverter with SVM. Note that, for six switch inverter, dc bus voltage is set to 75 V, while for nine-switch inverters; dc bus voltage is set to 150 V. It is seen that the reduced THD SVM has best harmonic performance for nine-switch inverters. As seen in Fig. 21, six-switch inverter has better harmonic performance. Fig.

8. (a) Line voltage of nine-switch-z-source inverter (simulation). (b) Line voltage of nine-switch-z-source inverter (experimental), (50 V/DIV, 10 ms/DIV). Authorized licensed use limited to: Bharat University.

Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply. DEHGHAN DEHNAVI et al. : SPACE VECTORS MODULATION FOR NINE-SWITCH CONVERTERS 1495 TABLE VIII NUMBER OF SEMICONDUCTOR SWITCHING Fig. 19. (a) Phase voltage of nine-switch-z-source inverter (simulation).

(b) Phase voltage of nine-switch z-source inverter (experimental), (50 V/DIV, 10 ms/DIV). Fig. 21.THD of load current of nine-switch inverter and six-switch inverter. Main reason is that in nine-switch inverter, active vectors are not centered within the switching period. VII. CONCLUSION In this paper, the SVM of nine-switch inverter and nineswitch-z-source inverter was proposed. Switching sequence of the proposed SVM is composed of the upper active vectors, the lower active vectors and the zero vectors.

The upper and lower active vectors are determined via two space vector diagram. The proposed SVM increases sum of modulation indices up to 15%, an important feature in providing higher torque for a given input dc-voltage.The proposed SVM is also developed for nineswitch-z-source inverter via extra shoot-through vectors. For both inverters, two SVM algorithms are developed to reduce THD and number of semiconductor switching. The proposed SVMs were simulated for both nine-switch inverter and z-source nine-switch inverter. An experimental setup was developed using a digital signal processor (DSP). The performance of the proposed SVMs was veri? ed using computer simulation, and it was validated using experimental data. APPENDIX Fig.

20. (a) Output currents of nine-switch-z-source inverter (simulation). b) Output currents of nine-switch-z-source inverter (experimental), (3 A/DIV, 10 ms/DIV). The sum of active vector time intervals must be less or equals to T . Thus (T1 + T2 + T3 + T4 ) ? T. Authorized licensed use limited to: Bharat University. Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore.

Restrictions apply. (A1) 1496 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 6, JUNE 2010 From (5)–(8) and (A1) we have mU sin ? ? ? U 3 + mU sin(? U ) + mL sin ? ? ? L 3 2 + mL sin(? L ) ? v . 3 (A2) The left term of (A2) can be divided to following two term: A = mU sin ? ? ? U 3 + mU sin(? U ), 0 ? U ? ? 3 (A3) B = mL sin ? ? ? L 3 [12] Y.

Tang, S. Xie, C. Zhang, and Z. Xu, “Improved Z-source inverter with reduced Z-source capacitor voltage stress and soft-start capability,” IEEE Trans. Power Electron. , vol. 24, no.

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4, pp. 833–838, Jul. 2005. + mL sin(? L ), 0 ? ?L ? ? . 3 (A4) The value of terms A and B changes regarding to ? U and ? L .

Equation (A2) should be true when the terms A and B have their maximum value. This happens when ? U = ? 6 and ? L = ? /6. Thus Am ax = mU sin ?? ? 3 6 + mU sin ? 6 = mU (A5) Bm ax = mL sin ?? ? 3 6 + mL sin ? 6 = mL .

(A6) Therefore, from (A2) 2 [ mU + mL ] ? v . 3 (A7) REFERENCES [1] T. Kominami and Y. Fujimoto, “A novel nine-switch inverter for independent control of two three-phase loads,” in Proc. IEEE Ind. Appl.

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1346–1355, Nov. 2005. Seyed Mohammad Dehghan Dehnavi (S’08) was born in Tehran, Iran, in 1981. He received the B. S.

degree from Azad Islamic University, Yazd, Iran, in 2003 and the M.S. degree from Tarbiat Modares University, Tehran, Iran, in 2005, both in electrical engineering. He is currently working toward the Ph. D. degree in the Department of Electrical and Computer Engineering, Tarbiat Modares University. His research interests include inverters, motor drives, inverter-based distributed generation, hybrid electric vehicle, and FACTS.

Mustafa Mohamadian (M’04) received the B. S. degree from AmirKabir University of Technology, Tehran, Iran, in 1989 and the M. S. degree from Tehran University, Tehran, in 1992, both in electrical engineering, and the Ph.

D. degree in electrical engineering, specializing in power electronics and motor drives, from University of Calgary, Calgary, AB, Canada, in 1997. Since 2005, he has been an Assistant Professor in the Department of Electrical and Computer Engineering, Tarbiat Modares University, Tehran. His current research interests include modeling, analysis, design and control of power electronic converters/systems, motor drives, embedded software development for automation, motion control, and condition monitoring of industrial systems with microcontrollers and digital signal processors.Ali Yazdian (M’95) was born in Tehran, Iran. He received the B. Sc. degree in electrical engineering from the Sharif University of Technology, Tehran, in 1989, the M.

Eng. (Hons. ) and Ph. D. degrees in electrical engineering from the University of Wollongong, Wollongong, N.

S. W. , Australia, in 1995 and 1999, respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering, Tarbiat Modares University, Tehran. His research interests include FACTS, power quality, power system protection, and information security.Farhad Ashrafzadeh (SM’06) received the B.

Sc. degree from Isfahan University of Technology, Isfahan, Iran, the M. Sc.

degree from Iran University of Science and Technology, Tehran, Iran, and the Ph. D. degree from the University of Calgary, Calgary, AB, Canada, in 1996, all in electrical engineering. He was a Postdoctoral Fellow at the University of Calgary for two years. In 1997, he joined Research and Development Center, Whirlpool Corporation, Benton Harbor, MI, where he was engaged in various capacities such as Electrical Drive Specialist,Global System/Technology Leader, and Global Intellectual Property Coordinator for the Electronics Organization at Corporate level.

He is currently a Staff Research Engineer and Global Technology Leader for the Advanced System Control and Estimation at the Research and Development Center, Whirlpool Corporation. He is also a certi? ed six-sigma Engineer, an Adjunct Professor, and a Member of the External Advisory Board for the Department of Mechanical and Aeronautical Engineering, Western Michigan University, Kalamazoo. He is the holder of 26 U. S. nd international patent applications and author of more than 24 technical articles. His research interests include applications of advanced electrical drives and power electronics in alternative energies and their interfacing with smart power grid. Dr. Ashrafzadeh is an Associated Editor for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS. He has also served as a Keynote Speaker for IEEE conferences and as an invited speaker for various universities and IEEE sections. Authorized licensed use limited to: Bharat University. Downloaded on June 10,2010 at 12:42:06 UTC from IEEE Xplore. Restrictions apply.