Iycee Charles de Gaulle Summary High Leakage Currents On Sram Cell Biology Essay

High Leakage Currents On Sram Cell Biology Essay

Decrease of escape current is important in low power applications. Because these escape currents increase the entire power ingestion of the circuit. In this paper, assorted bing escape decrease techniques for memory cells are discussed and besides a new 12T SRAM cell is proposed. These 12T SRAM cell has high stableness and low power ingestion compared to other cells. Some of the escape decrease techniques discussed in this paper are dynamic VDD, multiple Vth, double power supply strategy, SVL ( Self- Controllable Voltage Level ) and AVL ( Adaptive Voltage Level ) . These techniques are applied on different SRAM cells such as 6T, 7T, 8T, 10T and proposed 12T SRAM cell and the consequences are compared.

For simulation, MICROWIND 3.1 tool is used.Keywords-Leakage decrease, write ability, SRAM, escape power.I.INTRODUCTIONHigh escape currents on SRAM cell plays a major function in entire power ingestion of the low power memory cells. These leakage currents occur as a consequence of grading of the threshold electromotive force, channel length and gate oxide thickness. As engineering graduated tables down, the supply electromotive force, gate oxide thickness and channel length must be reduced.

We Will Write a Custom Essay Specifically
For You For Only $13.90/page!


order now

In future, the gate oxide thickness may be every bit low as 0.5nm for CMOS engineerings [ 1 ] . As a consequence, the decrease in gate oxide thickness additions gate leakage current.

The gate burrowing current is besides predicted to increase at a rate of 500 times per engineering whereas the sub-threshold current additions by merely 5 times [ 1 ] .As a consequence of high drain electromotive force and negative gate electromotive force, field crowding occurs at drain border doing gate induced drain escape ( GIDL ) . And besides this high drain electromotive force application to a short channel device consequences in take downing of barrier tallness and shifting of point of maximal barrier to the left doing drain induced barrier lowering ( DIBL ) .

If the supply electromotive force is below the threshold electromotive force, the procedure parametric quantities and the variableness of the SRAM addition badly [ 2 ] . Some of the SRAM stableness issues are process-induced device fluctuation, diminishing ION / IOFF and threshold electromotive force random fluctuation [ 3 ] .Due to increase in Vt fluctuations and procedure fluctuations, SRAM cell can non be operated at farther scaled supply electromotive forces without functional failures doing output loss.

A low-power 6T SRAM cell [ 4 ] shown in fig.1 could cut down entree hold and write power but could non better read stableness. A single-ended 6T SRAM cell [ 5 ] suffers from write hold.

File: SRAM Cell ( 6 Transistors ) .svgFig.1.

Basic 6T SRAM cell constructionThe paper is organized as follows:Section II explains about assorted escape currents happening in the transistor of SRAM cell. Section III presents assorted leakage current decrease techniques. In Section IV, the proposed 12T SRAM cell is discussed.

Section V presents the simulation consequences of the proposed techniques. Finally, decision is given in Section VI.II. LEAKAGE CURRENTS ON SRAMThe escape currents taking topographic point on the SRAM cells are sub-threshold escape current and gate escape current, negligible sum of DIBL and GIDL.A ) SUB-THRESHOLD LEAKAGE CURRENT:Fig.

2. Sub-threshold leakage current of MOSFETThe sub-threshold escape current takes topographic point between the drain and the beginning of the transistor. These leakage current happen when the gate electromotive force ( Vg ) is less than that of the threshold electromotive force ( Vth ) . The curve between gate beginning electromotive force ( VGS ) and the sub-threshold current ( ISUB ) is shown in fig. 2.

B ) GATE LEAKAGE CURRENT:The sub-threshold escape occurs merely on the inactive ( standby ) status. But, the gate escape current shown in fig. 3 takes topographic point on both ON and OFF province.As the engineering scaling consequences in the decrease of gate oxide thickness, a high electric field and tunnelling of negatrons between the substrate and gate takes topographic point. And this consequences in the gate oxide burrowing current.If positive prejudice is applied to the gate, the burrowing current flows from substrate to gate.

If negative prejudice is applied, burrowing occurs from gate to substrate.Gram: Gate current constituents fluxing between NMOS terminuss [ 1 ] .jpegFig.3. Gate escape currentC ) DIBL:The beginning and drain separation is big for long channel devices.

In long channel devices, the Vth is independent of the channel length and the drain electromotive force. But, in the short channel devices, the Vth is dependent on drain electromotive force i.e, Vth varies with regard to the drain electromotive force. This is known as Drain induced Barrier Lowering ( DIBL ) .D ) GIDL:Gate Induced Drain Leakage ( GIDL ) arises due to the high electric field happening in the drain junction of the transistor. It chiefly happens in the OFF province.

The high drain electromotive force and the negative gate electromotive force develop field herding at the drain border. This procedure consequences in gate induced drain escape known as IGIDL.III. LEAKAGE CURRENT REDUCTION TECHNIQUESThe different techniques employed for cut downing the escape current in SRAM cells are a ) Dynamic VDD B ) Multiple Vth degree Celsius ) Dual Power Supply Scheme vitamin D ) SVL vitamin E ) AVL.A ) Dynamic VDD Technique:In the dynamic VDD strategy, normal supply electromotive force is given to the circuit during the active manner.

But in the standby status, reduced supply electromotive force is given. For this procedure, an excess peripheral circuitry known as the efficiency electromotive force convertor is needed [ 6 ] . These reduced supply electromotive force decreases the escape current. But the supply electromotive force decrease, consequences in low SNM ( Inactive Noise Margin ) and besides causes informations tossing failures.

B ) Multiple Vth Scheme:The multiple Vth strategy consists of both high and low threshold transistors in the same bit which can be used for covering the escape job. The high threshold transistors are used for stamp downing the sub-threshold escape current and the low threshold transistor is used for accomplishing good public presentation.The undermentioned methods are used for accomplishing multiple threshold electromotive forces: I ) Multiple channel doping two ) Multiple oxide CMOS three ) Multiple channel length four ) Multiple organic structure prejudice.C ) Dual Power Supply Scheme:The engineering scaling requires the supply electromotive force to be reduced in order to cut down the power ingestion. But, the lowering of supply electromotive force consequences in worsened SRAM stableness.

In order to get the better of this job, excess power supply was used in many designs [ 12 ] [ 13 ] .Fig.4 Circuit for double power supply strategyIn 6T SRAM cell, the cell with higher VDD have better read stableness but worsened write stableness. In order to better the write ability, word line compensation technique is combined with double power supply strategy [ 11 ] . Two planetary power supplies viz. VSM and VDD are used in the fig.4.

D ) SVL Scheme:The SVL ( Self governable Voltage Level ) circuit employed on 10T SRAM cell is shown in the fig. 5.The basic construct is that when the SRAM cell is in active manner, the escape current is low. And there is no debasement in noise border. During standby manner, escape current is high and therefore reduced supply electromotive force is given to the SRAM cell. This reduces the escape current and besides reduces noise border.The major drawback of this technique is that it can non able to cut down the gate escape current.Fig.

5. 10T SRAM cell with SVL circuitTocopherol ) AVL Scheme:The AVL ( Adaptive Voltage degree ) strategy can able to cut down both the sub-threshold escape every bit good as gate escape current.In this technique, an AVL circuit is attached to the SRAM cell for commanding the effectual electromotive force across it. The AVL switch can be inserted either at the land node ( AVLG ) or supply node ( AVLS ) .The AVLG circuit will supply 0V at land node during the active manner and increased electromotive force during the standby manner [ 7 ] . This strategy is similar to that of the rectifying tube footed cache design strategy for commanding the escapes in SRAM.

In that, a rectifying tube is designed with high threshold transistor for raising the land degree in standby manner [ 8 ] . The 10T SRAM cell with AVLG circuit is shown in the fig. 6.

And the 10T SRAM cell with AVLS circuit is shown in fig. 7.Fig.6 10T SRAM cell with AVLG circuitFig.7. 10T SRAM cell with AVLS circuitIV.

PROPOSED 12T SRAM CELLThe basic SRAM cell consists of storage cell holding four transistors ( M1- M4 ) and two control transistors M5 and M6. In the proposed 12T SRAM cell, eight transistors for storage cell and four for entree control is proposed. These can be used for multiport application, as it can accept multiple inputs at a clip. The 12T SRAM cell is shown in the fig.8.Degree centigrades: UsersHemaDesktoppaperregconference12t.pngFig.

8 Proposed 12T SRAM cellV. SIMULATION RESULTSThe simulation consequences of the proposed techniques ( AVL and SVL ) are discussed in this subdivision. These techniques are employed on the proposed SRAM cells.Power ingestion of the conventional ( 6T, 7T, 8T and 10T ) SRAM cells is shown in the tabular array 1. Simulation consequences are simulated on MICROWIND tool under different supply electromotive forces.

Table.1. Power ingestion of assorted SRAM cellsCELL TYPESupplyVoltage( V )SumPower( W )Average DRAIN CURRENT( A )6T SRAM1.

20.19 m0.16 m0.51.45 Aµ0.003 m0.250.03 Aµ07T SRAM1.

20.19 m0.16 m0.50.64 Aµ0.001 m0.250.02 Aµ08T SRAM1.

20.43 m0.39 m0.

51.96 Aµ0.004 m0.

250.04 Aµ010T SRAM1.20.

21 m0.18 m0.50.93 Aµ0.

002 m0.250.02 Aµ012T SRAM1.20.11m0.092m0.50.

363 Aµ0.001m0.250.

023 Aµ0The power ingestion of the AVL ( AVLG & A ; AVLS ) and SVL ( SVL lower & A ; upper ) techniques is shown in the tabular array 2.Table.2. Power ingestion of Proposed SRAM cell utilizing assorted techniquesTechniqueSupplyVoltage( V )Entire Power( W )Average DRAINCurrent( A )AVLG1.20.14 m0.12 m0.

50.91 Aµ0.002 m0.250.02 Aµ0AVLS1.

20.50 Aµ0.005 m0.50.06 Aµ0.001 m0.250.02 Aµ0SVL upper1.

24.69 Aµ0.006 m0.50.14 Aµ0.001 m0,250.03 Aµ0SVL lower1.

20.14 m0.12 m0.50.

84 Aµ0.002 m0.250.03 Aµ0The end product wave form of the 10T SRAM cell is shown in fig. 9. In the wave form, three control lines are used viz.

spot ( in1 ) , bit_ ( in2 ) and word ( in3 ) as shown in fig.5. If the in3 is 0, both Q and nQ ( out1 and out2 ) will be zero.When in3 is 1, in1 is 0 and in2 is 1, out2 will be high and write operation is performed.

When in3 is 1, in2 is 0 and in1 is 1, out1 is high and read operation is performed.Fig.9. Output wave form of 10T SRAM cellThe layout of 10T SRAM cell is shown in the fig. 10.Fig.10. Layout of 10T SRAM cellThe electromotive force and current wave forms of 10T SRAM cell is shown in the fig.

11. The power ingestion is about 0.210mW and mean drain current ( Idd ) is 0.175mA.Fig.11. Voltage and current wave forms of 10T SRAM cellThe layout of 10T SRAM cell with AVLG is shown in the fig.

12.Fig.12. Layout of 10T SRAM cell with AVLGThe electromotive force and current wave forms of 10T SRAM cell with AVLG is shown in fig.13. The power ingestion is about 0.

141mW and the mean drain current ( Idd ) is 0.118mA.Fig.13. Voltage and current wave form of 10T SRAM cell with AVLG circuitThe layout of 10T SRAM cell with AVLS is shown in fig.14 and its electromotive force and current wave forms are shown in fig.16. The power ingestion is about 0.

504AµW. These consequences show that the power ingestion of the 10T SRAM cell reduces much with the AVLS technique compared to AVLG technique. The mean drain current ( Idd ) is besides reduced to 0.005mA compared to the conventional SRAM cells.Fig.14.

Layout of 10T SRAM cell with AVLSFig.15. Voltage and current wave form of 10T SRAM cell with AVLS circuitThe electromotive force vs clip wave forms of 10T SRAM cell with SVL lower and upper is shown in fig.16 and 17. The power ingestion is about 0.142mW and 4.699AµW and the mean drain current ( Idd ) is 0.

119mA and 0.006mA.Fig.16.

Voltage vs clip wave form of 10T SRAM cell with SVL lower circuitFig.17. Voltage vs clip wave form of 10T SRAM cell with SVL upper circuitThe layout of 10T SRAM cell with SVL lower and upper is shown in fig.18 and 19.Fig.18.

Layout of 10T SRAM cell with SVL lowerFig.19. Layout of 10T SRAM cell with SVL upperVI.

DecisionMany researches have been conducted on SRAM escape current decrease and stableness betterment. Some techniques focus merely on one portion of the job and present another job. The drawbacks of the assorted techniques are besides mentioned in this paper. Of the several escape decrease techniques discussed in this paper, SVL and AVL techniques show greater escape stamp downing capableness. For the stableness betterment of SRAM, spot interleaving technique improves both write and read ability of the SRAM in a better manner compared to other techniques.

The proposed 12T SRAM cell consumed low power compared to other cells.VII. ReferenceInternational engineering Roadmap for the Semiconductors [ online ] . Available: hypertext transfer protocol: //public.itrs.net.

S. Hanson, B. Zhai, K. Bernstein, L.Chang, D.Blaauw, A.

Bryant, K.K. Das, W. Haensch, E.J.

Nowak and D.M. Sylvester, “ Ultralow-Voltage minimum-energy CMOS, ” IBM J.Res.Develop. , vol. 50, no. 4/5, pp.

469-490, jul./sep. 2006.

H. Yamauchi, “ A treatment on SRAM circuit design tendency in deeper nanometer-scale engineerings, ” IEEE Trans. Very Large Scale Integr. ( VLSI ) Syst. , vol. 18, no. 5, pp.

763-774, May 2010.H. Mizuno and T. Nagano, “ Driving source-line cell architecture for sub- 1-V high-velocity low-power applications, ” IEEE J. Solid-State Circuits, vol. 31, no.

4, pp. 552-557, Apr. 1996.J.

Singh, D. K. Pradhan, S. Hollis, and S.P. Mohanty, “ A individual ended 6T SRAM cell design for ultra-low-voltage applications, ” IEICE Electron. Exp.

, vol. 5, no. 18, pp. 750-755, Sep.

2008.G. Fukano, K.

Kushida, A. Tohata, Y. Takeyama, K.

Imai, A. Suzuki, “ A 65nm 1Mb SRAM macro with dynamic electromotive force grading in double power supply strategy for low power SoCs, ” International Conference on Memory Technology and Design, Opio, pp. 18-22.Monika Yadav, Shyam Akashe, Yogesh Goswami, “ Analysis of escape decrease techniques on different SRAM cells, ” International Journal of Engg. Tendencies and Tech. , vol.

2, issue 3, pp. 78-83, 2011.Amit Agarwal, Hai Li and Kaushik Roy, “ DRG-Cache: A information keeping gated-ground cache for low power ” , Proceedings of the 39th Design Automation conference, June 2002.K. Nii, M. Yabuuchi, Y.

Tsukamoto, “ A 45-nm majority CMOS embedded SRAM with improved unsusceptibility against procedure and temperature fluctuations, ” IEEE J. Solid-State Circuits, vol. 43, pp. 180-191, Jan. 2008.

K. Nii, M. Yabuuchi, Y. Tsukamoto, , “ A 45-nm single-port and dual-port SRAM household with robust read/write stabilising circuitry under DVFS environment, ” in Proc. VLSI Circuits Symp. , pp. 212-213, Jun. 2008.

O. Hirabayashi, A. Kawasumi, A.Suzuki, “ A process-variation tolerant dual-power-supply SRAM with 0.179mm2 cell in 40nm CMOS utilizing level-programmable wordline driver, ” ISSCC Dig. Tech. Documents, pp.

458-459, Feb. 2009.K. Zhang, U.

Bhattacharya, Z. Chen, “ A 3-GHz 70-Mb SRAM in 65-nm CMOS engineering with incorporate column-based dynamic power supply, ” IEEE J. Solid-State Circuits, vol. 41, pp. 146-151, Jan.

2006.Saibal Mukhopadhyay, Rahul M. Rao Jae-Joon Kim, and Ching-Te Chuang, “ SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage, ” IEEE trans. On VLSI systems, vol. 19, no. 1, pp.

24-32, Jan. 2011.Ming-Hung Chang, Yi-Te Chiu and Wei Hwang, “ Design and Iso-Area Vmin Analysis of 9T Sub-threshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS, ” IEEE trans. on ckt.

& A ; systems, vol. 59, no. 7, Jul. 2012.